A Symbol Synchronization Lock Detector and Snr Estimator for Qpsk, with Application to Bpsk

This paper introduces a new lock detector for symbol timing recovery PLLs in QPSK receivers operating in AWGN channels. The detector necessitates only two samples per symbol, and these samples correspond to those required by the popular Gardner[1] timing error detector. The lock detector is characterized theoretically and through simulations. It transpires that the lock detector is selfnormalizing, and that the channel ES/N0 ratio can be accurately and easily estimated from the lock detector’s value. A simple hardware structure is found for the lock metric computation process, which allows for its compact implementation in an FPGA or ASIC. The analysis is then briefly generalized to apply to BPSK.